2nd course in the FPGA Design for Embedded Systems Specialization
Instructors: Timothy Scherr, MSEE, Senior Instructor & Benjamin Spriggs, MBA, MSEE, Lecturer
This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use them for design entry and verification with FPGAs and ASICs. You will use current HDL software tools for FPGA development, and practice with several programming examples that will give you proficiency with the languages. If you are thinking of a career in Electronics Design or looking at a career change, this is a great course to enhance your career opportunities.
Prior knowledge needed: ECEA 5360 Introduction to FPGA Design for Embedded Systems, knowledge of assembly and C Programming, Digital Logic Design, and basic computer architecture. Students should have a first course in each of these subjects. The corresponding CU-Boulder courses are ECEN 2120/2350, ECEN 3100/3350, and ECEN 1030/1310/CSCI 1300. To be specific, you are expected to be able to perform tasks similar to designing sequential circuits using Karnaugh maps or Boolean equations.
Syllabus
To learn about ProctorU's exam proctoring, system test links, and privacy policy, visit www.colorado.edu/ecee/online-masters/current-students/proctoru.
Grading
Assignment |
Percentage of Grade |
Week 1: VHDL Find the Code Errors Quiz |
2% |
Week 1: Module 1 Quiz |
5% |
Week 1 Programming Assignment: VHDL 2-bit Comparator |
2% |
Week 1 Programming Assignment: VHDL Correct Errors |
2% |
Week 1 Programming Assignment: VHDL Majority Vote |
2% |
Week 1 Programming Assignment: VHDL 1-bit Full Adder |
2% |
Week 2: Module 2 Quiz |
5% |
Week 2 Programming Assignment: VHDL 74LS163 Binary Counter |
2% |
Week 2 Programming Assignment: VHDL Make a Memory |
2% |
Week 2 Programming Assignment: VHDL Finite State Machine |
2% |
Week 2 Programming Assignment: VHDL ALU |
2% |
Week 2 Programming Assignment: VHDL FIFO |
2% |
Week 3: Verilog Find the Errors Quiz |
2% |
Week 3: Module 3 Quiz |
5% |
Week 3 Programming Assignment: Verilog 2-bit Comparator |
2% |
Week 3 Programming Assignment: Verilog Correct Errors |
2% |
Week 3 Programming Assignment: Verilog Majority Vote |
2% |
Week 3 Programming Assignment: Verilog 1-bit Full Adder |
2% |
Week 4: Module 4 Quiz |
5% |
Week 4 Programming Assignment: Verilog 74LS163 Binary Counter |
2% |
Week 4 Programming Assignment: Verilog Make a Memory |
2% |
Week 4 Programming Assignment: Verilog Finite State Machine |
2% |
Week 4 Programming Assignment: Verilog ALU |
2% |
Week 4 Programming Assignment: Verilog FIFO |
2% |
Week 5: ECEA 5361 Hardware Description Languages for FPGA Design Final Exam |
32% |
Week 5: ECEA 5361 Final Exam Programming Assignment #1 |
4% |
Week 5: ECEA 5361 Final Exam Programming Assignment #2 |
4% |
Letter Grade Rubric
Letter Grade |
Minimum Percentage |
A |
92% |
A- |
90% |
B+ |
87% |
B |
83% |
B- |
80% |
C+ |
77% |
C |
73% |
C- |
70% |
D+ |
67% |
D |
60% |
F |
0% |
Component List
You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, older ones may be upgraded.
The DE10-lite will be used as target board in this course.
These examples will not require the purchase of a development kit although the example target is relatively inexpensive ($55 Academic Price) and the first one on the list below. The other boards are also useful for further investigation and may be more available: