3rd course in the FPGA Design for Embedded Systems Specialization

Instructors: Timothy Scherr, MSEE, Senior Instructor​ & Benjamin Spriggs, MBA, MSEE, Lecturer​

The objective of this course is to learn how to develop, program, and use Softcore Processors with associated IP integration. To accomplish this, the Nios II Softcore Processor from Intel Altera is developed as an example design. The development flow is explained including both hardware and software development. Hardware is designed using the Qsys system design tool. Software is developed using an Eclipse-based IDE and Board Support Package Editor. One advantage of Softcore Processors is the ability to add a custom instruction, and this is demonstrated building it in hardware and using it in software. The range of IP available for various FPGA vendors is presented, along with the use of simulation to verify the designs. 

Prior knowledge needed: ECEA 5360 Introduction to FPGA Design for Embedded Systems, ECEA 5361 Hardware Description Languages for FPGA Design, knowledge of assembly and C Programming, Digital Logic Design, and basic computer architecture. Students should have a first course in each of these subjects. The corresponding CU-Boulder courses are ECEN 2120/2350, ECEN 3100/3350, and ECEN 1030/1310/CSCI 1300. To be specific, you are expected to be able to perform tasks similar to designing sequential circuits using Karnaugh maps or Boolean equations.

Learning Outcomes

  • Acquire an understanding of programmable systems on a chip for the purpose of creating prototypes or products for a variety of applications. 
  • Understand the use and proper application of Soft Processors for FPGAs. 
  • Create a Nios II Soft Processor, including both hardware and software design examples.
  • Understand and practice all aspects of FPGA development, including conception, design, implementation, and debugging. 
  • Learn specifics around embedded IP and processor cores, including tradeoffs between implementing versus acquiring IP.
  • Explore a number of example designs using FPGA development tools.


Duration: 2 hours

This module introduces the concept of a soft processor in general, and of hardware design for the soft processor in particular. It presents an overview of soft processors, describing all the different kinds that are available from Xilinx, Altera, Microsemi, and Lattice and then goes into depth about the Nios II soft processor from Altera. The benefits of using soft processors to prevent obsolescence and provide flexibility are explained. The content guides you through a hardware design of the Nios II processor using Qsys, the Altera system design tool. Lastly, design of a custom instruction in the Nios II is presented, showing the versatility of the soft processor in an FPGA.

Duration: 3 hours

This module delves further into the development of soft processors, It describes the soft processor development flow in more detail, including the tools needed to develop software for the soft processor. It then introduces the Eclipse-based IDE for Nios II software development, and then shows how the output of the Qsys design is used to establish a Board Support Package (BSP) for the processor, which is necessary because the processor hardware design can be changed and the BSP software library must support any changes. Use of the BSP editor to configure the processor by programming control registers is demonstrated. Finally, the use of the custom instruction developed in Module 1 is presented, including the use of software macros to complete the implementation of the custom instruction.

Duration: 2 hours

Modern FPGA design is no longer centered on HDL module design as it is on acquisition and use of IP Cores. In this Module we will introduce IP cores including offerings from all the major vendors, Intel Altera, Xilinx, Microchip Microsemi, and Lattice. You will learn how to find, acquire, and use these cores.

Duration: 4 hours

As we work on more complex FPGA designs, the challenges to create an error-free design mount exponentially. Having a good grasp of the tools needed to verify correctness of design has become more and more important. After introducing simulation in previous sessions, in this module we will examine simulation with ModelSim in more depth by working through some examples. This will show the utility of simulation for verification and debugging. This module will also describe in some detail how the simulator works and how it achieves concurrency through the use of delta delays. As a final step in the debugging process, the internal logic analyzer SignalTap II is introduced.

Duration: 2 hours

Final Exam for this course.

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Percentage of Grade
Module 1 Quiz 15%
Module 2 Quiz 15%
Module 3 Quiz 15%
Module 4 Quiz 15%

ECEA 5362 FPGA Softcore Processors and IP Acquisition Final Exam


Letter Grade Rubric

Letter Grade 
Minimum Percentage























Component List

You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, older ones may be upgraded.

The DE10-lite will be used as target board in this course.

These examples will not require the purchase of a development kit although the example target is relatively inexpensive ($55 Academic Price) and the first one on the list below. The other boards are also useful for further investigation and may be more available: