1st course in the FPGA Design for Embedded Systems Specialization

Instructor: Timothy Scherr, MSEE, Senior Instructor​

This course will give you the foundation for FPGA design in Embedded Systems. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development and solve critical digital design problems using FPGAs. If you are thinking of a career in Electronics Design or looking at a career change, this is a great course to enhance your career opportunities.

Prior knowledge needed: Knowledge of assembly and C Programming, Digital Logic Design, and basic computer architecture. Students should have a first course in each of these subjects. The corresponding CU-Boulder courses are ECEN 2120/2350, ECEN 3100/3350, and ECEN 1030/1310/CSCI 1300. To be specific, you are expected to be able to perform tasks similar to designing sequential circuits using Karnaugh maps or Boolean equations.


Duration: 5 hours

What's this programmable logic stuff anyway? In this Module, you will learn about the history and architecture of programmable logic devices including Field Programmable Gate Arrays (FPGAs). You will learn how to describe the difference between an FPGA, a CPLD, an ASSP, and an ASIC; recite the historical development of programmable logic devices; and design logic circuits using LUTs. Examples will include designs of digital adders and multipliers in FPGAs.

Duration: 4 hours

In this Module  you will install and use sophisticated FPGA design tools to create an example design. You will learn the steps in the standard FPGA design flow, how to use Intel Altera’s Quartus Prime Development Suite to create a pipelined multiplier, and how to verify the integrity of the design using the RTL Viewer and by simulation using ModelSim. Using the TimeQuest timing analyzer, you will analyze the timing of your design to achieve timing closure.

Duration: 4 hours

FPGAs are programmable, and the program resides in a memory which determines how the logic and routing in the device is configured. In this Module you will learn the pros and cons of FLASH-based, SRAM-based, and Anti-Fuse based FPGAs. A survey of modern FPGA architectures will give you the tools to determine which type of FPGA is the best fit for a design. Architectures will be explored from the basic core logic cell up to consideration of large Intellectual Property (IP) blocks that are available on many FPGAs.

Duration: 6 hours

In this Module you will extend and enhance your design from module 2, completing the design by adding IP blocks, implementing pin assignments and creating a programming file for the FPGA. One outcome will be improved design productivity, by the use of design techniques like pipelining, and by the use of system design tools like Qsys, the system design tool in Quartus Prime. You will complete a Qsys system design by creating a NIOS II softcore processor design, which quickly gives you the powerful ability to customize a processor to meet your specific needs.

Duration: 2 hours

This module contains materials for the proctored final exam for MS-EE degree students. If you've upgraded to the for-credit version of this course, please make sure you review the additional for-credit materials in the Introductory Module and anywhere else they may be found.

To learn about ProctorU's exam proctoring, system test links, and privacy policy, visit www.colorado.edu/ecee/online-masters/current-students/proctoru.


Percentage of Grade

Mission 001: Week 1 Application Assignment


Mission 002: Week 1 Quiz


Mission 004: Week 2 Application Assignment


Mission 005: Week 2 Quiz


Mission 006: Week 3 Quiz


Mission 007: Week 4 Application Assignment


Mission 008: Week 4 Quiz


ECEA 5360 Introduction to FPGA Design for Embedded Systems Final Exam


Letter Grade Rubric

Letter Grade 
Minimum Percentage























Component List

You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, older ones may be upgraded.

A target FPGA development board, while helpful, is NOT required for this course.

These examples will not require the purchase of a development kit although the example target is relatively inexpensive ($55 Academic Price) and the first one on the list below. The other boards are also useful for further investigation and may be more available: