4th course in the Real-time Embedded Systems Specialization.

Instructor: Sam Siewert, Ph.D., Associate Professor Adjunct 

In this course, students will design and build a microprocessor-based embedded system project managing real-time constraints while analyzing the system in-order to meet them.

Students are expected to do a project capturing the images from a camera connected to raspberry pi at 1 Hz and 10 Hz frequency while storing them in the memory. Various problems encountered while designing the system and its proper documentation is expected from the students.

Prior knowledge needed: ECEA 5315 Concept and Practices, ECEA 5316 Theory and Analysis, ECEA 5317 Mission-Critical, SW Applications, C Programming and Compilation Pipeline, Computer System Architecture, Operating Systems Concepts, Linux based Systems


Duration: 11 hours

This module provides background on the RTES project including the concept of a "visual synchronome", where a camera is used to synchronize time between an external clock and an embedded computer.  The project requires synchronization at both 1 Hz and 10 Hz, where the real-time services must acquire camera frames, select stable (non-blurred) frames and write them to a flash file system. The project requires a good understanding of RMA, real-time scheduling, and design principles for multi-service real-time systems.

Duration: 9 hours

Different design approaches for the RTES project are reviewed in this module including the "shot gun" start, where clock ticks are detected once at the start, the full synchronome continuous tick detection approach, and different options for implementation.  RTES project designers must decide on a camera interface, for example a V4L2 (Video for Linux 2) interface to UVC (Universal Video Controller) driver, or an OpenCV interface to a camera.

Duration: 10 hours

To ensure that a real-time design is properly implemented, timing analysis based upon system logging and tracing must be used to verify that actual timing compared to theoretical RMA. This module provides and overview of methods and suggests the most efficient methods to debug and verify timing of the RTES project. The module includes a 1 Hz peer review of design and code to assist with RTES project improvement for external clock synchronization using camera images with a ticking analog clock.

Duration: 10 hours

This module covers methods of tracing and profiling for the overall RTES project platform including networking, system profiling, and methods to trace real-time services in particular.  The module includes a 10 Hz peer review of design and code to assist with RTES project improvement for external clock synchronization with a digital stopwatch at this higher rate compared to 1 Hz.

Duration: 11 hours

The overall RTES project should be completed for this module.  Students can review tips and examples for how to prepare their design materials, their RMA, and code for review.  The process for inspection to verify and validate the design based upon the RTES project rubric is defined here as well.

Duration: 8 hours

Final exam for this course.

To learn about ProctorU's exam proctoring, system test links, and privacy policy, visit www.colorado.edu/ecee/online-masters/current-students/proctoru.


Percentage of Grade
Peer Review: Initial Services, RMA and Timing Diagrams 10%

Quiz: Basics of Real-Time Systems


Peer Review: Code Walk-through of Project Starter Code 10%
Quiz: Project Design, Implementation & Functional Testing 5%
Peer Review: 1 Hz Monotonicity and Glitch Free Operation 10%
Programming: Final Project Operation at 1 Hz 5%
Peer Review: 10 Hz Design Walk-through 10%
Programming: Final Project Operation at 10 Hz 5%
Peer Review: Final Design and RTES Solution Presentation 10%

Quiz: Project and Final Take-Away Major Concepts


Programming: Project Final Exam - 1 Hz Test 12.5%

Programming: Project Final Exam - 10 Hz Test


Letter Grade Rubric 

Letter Grade 
Minimum Percentage



A- 90%
B+ 87%



B- 80%
C+ 77%



C- 70%
D+ 67%