Group

“Proving properties for Bounded Model Checking” 2006.

“Methods for Timing Analysis and Logic Synthesis to Decrease Power Dissipation of VLSI Circuits,” 1995.

“Search Techniques and Automata for Symbolic Model Checking,” 2001.

“Reachability Analyses and Their Applications in Test Generation and Logic Optimization for Sequential Circuits,” 1993.

“Reachability Analyses and Their Applications in Test Generation and Logic Optimization for Sequential Circuits,” 1993.

“Efficient Solution of Satisfiability Problems in CAD Applications,” 1999.

“Efficient Algorithms for Finding All Satisfying Assignments of a Propositional Formula,” 2005.

“Layout Conscious Logic Optimization Techniques for Power and Delay Reduction in FPGAs,” 2000.

“Approximate Model Checking,” 1998.

“Satisfiability-based Abstraction Refinement in Symbolic Model Checking,” 2006.

“Efficient Reachability Algorithms in Symbolic Model Checking,” 2000.

“Proving Properties of Digital Systems with Abstraction-Guided Simulation,” 2009.

“Adaptive Techniques to Improve State Space Search in Formal Verification,” 1999.

“Finite State Models for the Optimization and Verification of Digital Systems,” 1993.

“Exploiting High-Level Design Control and Data Structures for Hardware Verification,” 2007.